The present invention relates to a method for forming an isolation structure of a semiconductor device, and more particularly, to a method for forming an isolation structure of a semiconductor device that can prevent an excessive loss of an isolation structure when forming a recess gate.
As semiconductor devices become more highly integrated, trench filling when forming an isolation structure for defining an active region has become a difficult issue. A method has been disclosed in the art for this situation in which a spin-on glass layer (hereinafter referred to as an “SOG layer”), with an excellent gap filling characteristic, is first deposited in the trench, and a high-density plasma-chemical vapor layer (hereinafter referred to as an “HDP layer”) is deposited on the SOG layer, such that the trench is filled by the stacked layer of the SOG layer and the HDP layer.
In this method, because the SOG layer with the excellent gap-fill characteristic fills a high percentage of the lower trench, it may be possible to prevent the formation of a void when completely filling the trench. Also, in this method, because the upper portion of the trench is filled by the HDP layer having a relatively slow etching speed, it may be possible to prevent the isolation structure from being damaged when subsequently conducting a cleaning process and an etching process.
Hereafter, a conventional method for forming an isolation structure of a semiconductor device will be described with reference to FIGS. 1A through 1D.
Referring to FIG. 1A, a buffer oxide layer 112 and a pad nitride layer 114 are sequentially formed on a semiconductor substrate 100 having an active region and a field region. By etching the pad nitride layer 114 and the buffer oxide layer 112, a hard mask 116, which comprises a stacked layer of the buffer oxide layer 112 and the pad nitride layer 114 and exposes the field region of the semiconductor substrate 100, is formed.
Referring to FIG. 1B, the exposed field region of the semiconductor substrate 100 is etched using the hard mask 116 as an etch mask, thereby defining a trench T. By conducting a thermal oxidation process, a wall oxide layer 122 is formed on the surface of the trench T. A liner nitride layer 124 is formed on the hard mask 116 including the wall oxide layer 122.
Referring to FIG. 1C, after an SOG layer 132 is deposited on the liner nitride layer 124, the deposited SOG layer 132 is etched back such that it remains only on the lower portion of the trench T.
Referring to FIG. 1D, an HDP layer 134 is deposited on the liner nitride layer 124 including the remaining SOG layer 132 to completely fill the trench T. The HDP layer 134 is subjected to chemical mechanical polishing (CMP) to expose the hard mask 116. By removing the hard mask 116, an isolation structure 140 is formed in which the trench T is filled with the stacked layer of the SOG layer 132 and the HDP layer 134.
Meanwhile, when manufacturing a sub-100 nm semiconductor device, in order to secure an effective channel length, a method of forming a recess gate is adopted. The recess gate is formed by defining a groove by etching a gate forming area on an active region of the semiconductor substrate, depositing a gate material on the semiconductor substrate including the groove, and etching the gate material.
However, in the conventional art, when conducting the etching process for defining the groove for the formation of the recess gate, as shown in FIG. 2, an undesired loss A is caused in the isolation structure 140 (see FIGS. 1D and 2). When the loss A is caused in the isolation structure 140 in this way, a short circuit occurs between adjoining gates, the threshold voltage decreases, and gate induced drain leakage (GIDL) increases. Further, if the loss A is caused in the isolation structure 140, the area of the isolation structure 140 which adjoins a gate increases, and parasitic capacitance also increases, whereby the operation characteristics of a semiconductor device are deteriorated, and yield decreases.
The loss of the isolation structure caused when forming a recess gate can be mitigated to some extent by increasing the deposition thickness of the HDP layer, which has a relatively slower etching speed than the SOG layer. Nevertheless, as the depth to which the HDP layer is to fill the trench increases, trench filling becomes more difficult. Consequently, as shown in FIG. 3, a void V is likely to form in the trench T. Therefore, increasing the deposition thickness of the HDP layer lacks practicality since a number of other problems are caused.